VLSI training in functional verification
VLSI training in functional verification
VLSI Front end training for Experienced Engineers (VG-FEDV) course is a 19 weeks course structured to enable experienced engineers gain expertise in functional verification. Majority cases, engineers does not get the hands on exposure to SV & UVM based testbench development, most of times goes in testcase coding and debug, leaving with very minimal SV & UVM expertise. This course is targeted for such engineers, to enable them get hands on exposure to complete Testbench development using SV & UVM.
Training includes more than 40+ assignments covering various aspects of Systemverilog, AXI Protocol, AXI VIP Development, Memory Controller verification, UVM constructs, AHB Protocol, AHB UVC Development and AHB Interconnect functional verification. All the aspects of the course are covered using practical examples. Systemverilog training involves more than 250+ examples covering all the aspects of Systemverilog. UVM training involves more than 100+ examples. All the examples and projects are developed from scratch as part of training sessions.
Course content is same as Systemverilog Training and UVM Training
SystemVerilog for Advanced Verification
- Classes : Object Oriented Programming
- Arrays, Data Types, Literals, Operators
- Scheduling Semantics, Inter process Synchronization
- Processes, Threads, Tasks and Functions
- Randomization, Constraints
- Interface, Clocking blocks, Program Block
- Functional Coverage
- Assertion Based Verification
- System Tasks & Functions
- Compiler Directives
- DPI
Verification IP Development
- AXI Protocol Concepts : Features, Signals, Timing Diagrams
- AXI VIP Architecture Development
- VIP Component Coding
- AXI Slave model test case development
- Test Case debugging
ASIC Verification Concepts
- SoC Verification Concepts
- Module Level Verification
- Constrained Random Verification
- Coverage Driven Verification
- Directed Verification
- Assertion Based Verification
Industry Standard Project : Memory Controller Functional Verification
- Reading Specification | Feature listing down | Scenario Listing down
- Functional coverage listing down | Coverage Implementation
- Testplan creation | Testbench architecture development
- Testbench component coding | Testcase coding
- Sanity testcase debug | Regression Setup | Regression Debug
- Verification closure using Regression, Functional & Code coverage
UVM
- UVM Base classes
- UVM Messaging
- Config db, resource db, factory
- Sequences
- UVM Testbench Architecture
- AHB2.0 Protocol | AHB UVC development
- AHB Interconnect functional verification
Course Assignments
40+ detailed assignments covering all aspects of SV & UVM.
| Course | VLSI frontend training for experienced engineers |
|---|---|
| Duration | 19 weeks |
| Schedule | Saturday & Sunday(8:30AM – 4:00PM India time) |
| 8:30AM – 12PM (Trainer led theory and lab sessions) | |
| 1PM to 4PM (Mentor guided lab & assignment solving sessions) | |
| New batch starts | every 7 weeks |
| Fee | INR 32000 (Classroom Training) |
| INR 38000 (Online Training) | |
| Tool | Questasim & VCS |
| Mode of training | Classroom training at Institute |
| Online training using live training sessions | |
| Tool Access | Tool access for 1 year duration |
| Certificate | Issued based on 50% assignment completion as criteria |
| Admission criteria | Student need to undergo evaluation test based on Verilog Digital Design and Aptitude |
| Assignments | 40 |
| Trainer | 12+ Years exp in RTL design & Functional verification |
Below is the list of projects student will be doing as part of 19 weeks training. Institute provides guidance(trainer will be doing all these projects) on all these projects. If student gains expertise in these projects, learning will be on-par with a 2 to 3 years experienced engineer, in terms of skill set required. Student can work on additional projects, if he/she wants to enhance resume for experienced job role.By working on below projects, student will get familiar with:
- majority of standard protocols(AXI, AHB, APB, SDRAM, Ethernet, etc)
- Industry standard simulation tools like Questasim & VCS
- RTL debug expertise
- RTL coding and TB development
Project#1: Memory Controller Functional Verification using System Verilog
Design supports SDRAM, SSRAM, Flash & Synchronous Chip select devices. As part of this design verification, we created testbench using SV to generate scenarios targeting all types of supported memories for different possible combinations & different sizes supported. We also developed monitor, reference model & checker as part self-checking testbench implementation.
Responsibilities
- Listing down design features
- Setting up Testbench and testbench component coding.
- Testplan development
- Testcase coding
- Regression setup and debug
Project#2: Verification IP Development for AXI3.0 protocol using SV
AXI3.0 is an AMBA protocol used for high performance applications. AXI3.0 supports various features like out of order transactions, burst transfers, cacheble and bufferable transactions few among various features supported. VIP was developed to work as both master and slave. Developed all the VIP components and validated VIP for various AXI features.
Responsibilities:
- Develop VIP Architecture to be compatible with both master and slave behavior
- List down AXI features and develop testplan for validating AHB VIP
- Develop AXI VIP components
- Integrated AXI Master VIP with slave VIP
- Develop sanity testcases and debug the same
- Develop functional tests and debug the same
- Regression setup and closing of VIP validation using coverage criteria
Project#3: UVC Development for AHB2.0 protocol using SV & UVM
AHB2.0 is an AMBA protocol used for medium performance applications. I was part of UVC development team. UVC was developed to work as both master and slave. Developed all the UVC components and validated UVC for various AHB features.
Responsibilities:
- Develop UVC Architecture to be compatible with both master and slave behavior
- List down AHB features and develop testplan for validating AHB UVC
- Develop AHB UVC components
- Integrated AHB Master UVC with slave UVC
- Develop sanity testcases and debug the same
- Develop functional tests and debug the same
- Regression setup and closing of UVC validation using coverage criteria
Project#4 : Ethernet Switch design verification using SV
Ethernet switch is a design with multiple ingress and multiple egress ports. Switch parses the packets coming on ingress port and routes them on corresponding egress port based on Destination address. I was responsible for setting up the complete TB environment including development of various TB components, reference model and checker.
Project#5: AHB Interconnect Functional verification using SV & UVM
AHB Interconnect is a design with configurable number of masters and slave interface. Design routes the AHB transactions at master interfaces to corresponding slaves. I was responsible for setting up configurable TB using SV & UVM for interconnect verification. I have also developed testcases and sequences for verifying various design features.
What are the Course Prerequisites?
- Expertise on Verilog programming
My college curriculum covers most of these topics, why should I opt for this course?
- Course content covered in college(Btech/Mtech) curriculum is mostly theoretical and does not cover practical aspects. This course helps address that gap.
Does course cover practical sessions on SystemVerilog usage?
- Each aspect of course is supported by lot of practical examples
- Ethernet loopback design used as reference design from Session#1 towards implementing and learning SystemVerilog constructs
- All SystemVerilog course examples, AXI VIP, and Memory Controller Verification environment implemented from scratch as part of sessions
- Dedicated full day lab sessions to ensure student does complete testbench development from scratch
Is it possible to cover so many things in 17 weeks?
- We have done it for 35 Batches so far, next batch is no exception
- Course requires student to spend at least 6+ hours of time a week to revise the concepts
What if I miss few sessions during course?
- Each session of course is recorded, missed session videos will be shared
Course has started few weeks back, can I still join the course in between?
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
Do you offer support after course completion?
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail your queries
- Option to meet trainer in person to clarify doubts
Trainer Profile
- 12+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Subsystems
- Experience of working on multiple complex module level projects
After the successful completion of the course certificate will be issued.