Verilog And Advanced Digital Training

(Classroom & Online live Training)

Course Schedule & Fee:

• Course: VLSI summer training cum internship
• Location: Bangalore & Noida
• Duration : 6 Weeks | Schedule : 6 days per week, 5 hours per session
• Fee : INR 9,000 (all inclusive)
• Course start date : 01/June
• Demo Session: 1/June, 9AM to 1PM
• Offered in both classroom and online

Course Contents:

• Verilog for Design and Verification

       Verilog Language Constructs

• Introduction to Verilog HDL |  Module   | Data Types | Verilog Operators
• Dataflow Modelling | Behavioral Modelling | Gate Level Modelling
• Structural Modelling | Operators | Assignment Statements | procedural statements | always | initial | delay modelling | compiler directives | System Tasks & functions | Compiler Directives |File Input & Output | State Machines | Verilog Registers | Table | Primitives | Generate | Systems tasks & functions | Synthesis | PLI & VPI | | Design implementation using RTL | Testbench coding

     Design & Verification Projects covered (Tool used: Mentor graphics Questasim)

• Flipflop & registers | Various Counters | PISO | POSI | Standard combinational circuits | Dual Port RAM | Pattern Detector |Vending Machine | Traffic Light controller | CRC generation
• Watchdog timer | Synchronous FIFO | Asynchronous FIFO | Interrupt Controller | SPI Controller | I2C Controller | UART Controller

Advanced Digital Design

Digital Design Syllabus

• Numbering system | Karnaugh maps | Timing diagrams | Pipelining | Flipflop
• Latch | Various types of FF’s, Latch’s | Various Counters (applications) | FIFO
• Data transfer synchronisation between components | Race condition
• Meta stability | Multiplexer, Using MUX to create various gates, FF | Decoder, encoder, priority decoder | Parity generation | Half adder, full adder | Truth table for HA, FA, Mux, counters | Buffer, inverter | PLL, VCO, clock generation
• Clock multiplication | Clock division | clock domain crossing | Reset | Power management in SOC | State machines | Register
• Memories | Synthesis | Predict design output | Gate level simulations
• Debugging incorrect designs | Clock distribution | Active low and active high
• PISO, SIPO | Comparator | Designing circuits for various requirements
• CRC calculation logic | Pattern detector FSM

Analog Design Training

• Basics & Introduction to domains of analysis(Time, Frequency, S-domain)
• MOSFETS I-V characteristics and operating point analysis | MOS Device Operation | RC Circuits | Threshold Voltage (Body Effect)
• Device Ron | MOS Device as Current Source & Sink | MOS Current Mirrors | Differential Amplifier & Two Stage Differential Amplifiers | Voltage & Current Reference Generators (BG) | Voltage Regulators Design Basic
• CMOS process technology | CMOS Based circuits
• Simple CMOS amplifier topologies | MOSFET in deep submicron technology
• Differential Amplifiers | Feedback | Understanding SPICE simulations(AC, DC, Transient, Noise)

After the successful completion of the course certificate will be issued.