Verilog For Design And Verification
Verilog For Design And Verification
Verilog for Design & Verification (VG-VERILOG) is a 7 weeks course with detailed emphasis on Verilog for complex design implementation and verification. VT-VERILOG course is targeted for both design & verification engineers to gain expertise in Verilog for design & testbench development. This is must do course for every electronics and electrical graduate.
Student may also opt for course on advanced digital design and basic analog design conceptsAdvanced Digital Design Training.
Course has been framed in a way to make Verilog learning a fun and interesting activity. Every aspect of course is supported with multiple examples to enable easier & quicker understanding. Course also covers multiple design implementation examples and testbench setup for the same, and all these executed from scratch. Lab sessions are planned at regular intervals to enable student work on these projects from scratch with trainer guidance. Below is quick overview of what is covered as part of VT-VERILOG
- Verilog language constructs with detailed examples on each construct usage
- Multiple Design Coding & Testbench development
- Access to Questasim tool
- Hands on labs & Hands on projects
- Basic Digital Design Concepts
- Advanced Digital Design Concepts
- Basic Analog Design Concepts
Verilog Language Constructs
- Verilog
- How Verilog differs from other programming languages?
- Verilog language concepts
- registers, nets
- Vectors, Array
- Memories
- Data types
- Operators
- Various styles of Modeling: Data Flow, Behavioral, Gate level, Switch level
- Procedural Blocks
- Continuous assignments
- Procedural Statements
- Generate
- State Machines
- Gate Level Implementation
- Hierarchical modeling
- Verilog Programming Interface(& PLI)
- Pipelining
- FSM : Mealy and Moore
- FSM State encoding styles
Commonly asked Verilog Design Examples : All covered in course training
- Flipflop (Synchronous & Asynch Reset), Latch
- Counter-Gray code counter, modulo, ring, johnson, up counter, down counter
- Shift register implementation
- Half adder, full adder, multiplexer
- Dual port memory write, read design & testbench
- encoder, decoder, various gates
- Primitive implementation using table, endtable
- Pattern detector
- Coin counter for tea vending machine
- Traffic light controller(TLC)
- CRC generation code
- Watchdog timer implementation
- Synchronous FIFO
- Asynchronous FIFO
- Memory implementation
- example to showcase race condition using blocking assignments
- system task usage: $display, $monitor, $strobe
- PLI, VPI implementation
- Memory controller RTL understanding, architecture understanding
- Clock generation with Duty cycle & Jitter
- PCIe different layer implementation
- Interrupt Controller
- SPI Controller
- I2C Controller
- UART Controller
Verilog for Verification
Verification of all above designs using Verilog
| Course | Verilog for Design & Functional Verification |
|---|---|
| Duration | 7 weeks |
| Schedule | ||
| Freshers | Full week course | |
| Saturday & Sunday(9AM – 5PM India time. Monday to Friday(9:30AM to 12:30PM). Flexible lab sessions for US Students. | ||
| Weekdays sessions will be focused on labs, course assignments, Digital design and interview focused sessions. | ||
| Students also get support on complete project flow during weekdays as well. | ||
| New batch starts | Every 7 Weeks | |
| Fee | INR 8000 (Classroom), INR 9000 (Online) | |
| Tool | Questasim | |
| Mode of training | Classroom training at Institute | |
| Online training using live training sessions | ||
| Certificate | Issued based on 50% assignment completion as criteria | |
| Batch Size | 20 | |
| Assignments | 16 | |
| Trainer | 12+ Years exp in RTL design & Functional verification |
What are the Course Prerequisites?
No per-requisites. Good to know C language & exposure to Digital Design concepts
Does course cover practical sessions on UVM usage?
- Each aspect of course is supported by lot of practical examples
- Dedicated full day lab sessions to ensure student does complete testbench development from scratch
Course has started few weeks back, can I still join the course in between?
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
Do you offer support after course completion?
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
Trainer Profile
- 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
- Experience of working on multiple complex module level projects
After the successful completion of the course certificate will be issued.