UVM for Functional Verification training (VG-UVM) course is a 7 weeks course structured to enable engineers develop skills in full breadth of UVM features in complex testbench development. UVM Training course is targeted towards engineers looking to explore functional verification techniques involving advanced methodology concepts like factory, databases and register layer. The course is targeted for engineers with all experience levels, starting from a BE, ME fresher to experienced engineers. UVM Training course is also targeted for engineers working in non-VLSI domains and planning to switch in to VLSI. Learning starts from basic examples to complex testbench development coding, to ensure a smooth learning curve.
UVM Training course is divided in to 3 aspects, covering language constructs, industry standard protocols(AMBA AHB, APB), UVC development for these protocols and multiple industry standard projects with complete flow starting from specification reading till functional verification closure using regression, functional and code coverage as closing criteria. Institute also offers more than 40+ other projects based on industry standard protocols like USB3.0, PCIe, UFS, SATA, DDR, DMA, AMBA, Bridge and Ethernet MAC etc. Student can opt for these projects at a nominal fee.
UVM constructs are learnt using more than 100+ detailed examples covering all aspects of UVM starting from base clases, uvm_root, messaging classes, policy classes, factory, configuration, resource data bases, TLM1.0, TLM2.0, sequences, sequence libraries, layered sequences, virtual sequences and sequencers, event, barrier pools and various advanced concepts like register layer, etc. AHB Interconnect design is used as a reference example to learn all above aspects of UVM. These examples cover more than 90% of questions asked in VLSI interviews.
UVM Training course also covers multiple hands-on verification projects based on AHB, APB, and AHB Interconnect. Learning starts from simple projects like AHB UVC development to complex design verification projects involving Functional verification of AHB Interconnect using SV & UVM. All these projects are done from scratch. Course curriculum also ensures that student also does these projects hands-on with trainer guidance as part of dedicated lab sessions.
UVM Training course also involves 20+ detailed assignments. Student will be provided with guidance in solving these assignments. Student progress is tracked using completion of assignments as a sole criteria. Student is offered with multiple interview opportunities based on performance in assignments.
Below is salient features of UVM for Functional Verification training course.
- UVM language constructs learning using 100+ detailed examples
- UVC development for AHB and APB protocols
- AHB Interconnect verification
- 20+ detailed assignments covering all aspects of UVM