Trainer Profile

• Multiple trainers, each with rich experience of SOC subdomain. All working in top-3 product companies.

FAQ:  

• Course pre-requisites?
  • Working knowledge of SV, capable of setting up testbench for simple designs
• What if few sessions missed?
  • We will cover up missed sessions
• Course has started few weeks back, can I still join the course in between?
  • Missed sessions will be covered up, option to repeat the course in next 1 year*

Course Content:

1. SOC design & verification flow overview
2. SOC Design concepts
3. Processor boot concepts
4. SOC Verification : Important aspects
5. Testbench
6. Setting up SOC TB environment
7. SOC Subsystem overview (Processor, High speed, Low speed, Modem, Multimedia subsystem)
8. Testplan
9. Testcase Flow
10. Testcase Coding (C & SV)
11. Running testcases & regression
12. SOC Test debug
13. Typical testcase issues
14. Verification closure
15. Performance requirements
16. Gate level simulations
17. Power Aware Simulations
    1. PAGLS
18. EVCD generation
19. Vector runs on VT setup
20. Generating binaries for running on tester
21. ECO
22. RMA
23. UVC in Testbench setup & sequence usage in SV testcase

1. SOC FLOW:

• SoC Architecture
• Design Integration
  • Spy glass,
• Functional Verification
• Formal Verification (Connectivity Checks)
• PA RTL simulations
• GLS
• PA GLS simulations (UPF)
• Vector evcd generation
• VT simulations on testers
• Post silicon validation (VI)

2. Design:

• SoC Architecture
• SoC Interconnects & NOCs
• NoC Overview – Types of NOCs, purpose and diagram
• SoC Digital & Analog Components
• SoC Address Mapping
• SoC Interrupt Mapping
• SoC Frequency Plan
• SoC Performance requirements
• Features
• DPLL
• SoC Memories: Msg ram, Iram, DDR, Flash
• SoC Subsystems
• Low Power Verification
  • UPF

3. Important aspects:

• SoC Architecture, understanding transaction matrix
• Processor boot, SCF file,
• interconnects
• Memory preloading
• DDR initialization
• PLL locking(LMN values)
• TIC interface
• Clock domains
• Different clock mode
• XO mode, at-speed mode
• Interrupt handler
• Processor interfaces: interfaces meant for fetching instruction, data code
• I/O’s of SOC: Dedicated IO’s, and GPIOs
• GPIO purpose : Pad muxing
• CDC
• Cycle slips
• MMU, Physical address, virtual address
• ARM instruction set basics
• Types of verification : how they are different
• Processor architectures
  • ARM, ARC, DSP
  • Cortex A series, M series
  • Impact on design architecture
• Basics of ARM processors
  • Types of processors – Cortex-M series, A series.
  • ARM C, ASM compiler, linker.
  • Caches (L1 and L2).
  •  
  • Generic Interrupt controller.
  • Exceptions, Events – Types of Exceptions (Edge, Level), Source of Exceptions, How to handle.
  • Debug system – Basics of ARM debug sub system.
  • Scatter files.
  • How to set reset location to start booting.
  • Loading C code into memories – Front door, back door.
  • ARM Instruction example

4. SOC Testbench Setup

• SoC environment structure
• SoC TB Architecture
• Integrating UVC in to SoC TB
• SoC Processor-TB interaction

5. Testplan:

• register wr-rd, reset tests
• Interrupt tests
• targeting different frequency plans
• Feature(use-case) tests
• power aware tests
• Fuse tests
• End to end data transfer tests
• Booting from different testcases
• Address decoding access tests
• Connectivity tests

6. Testcase Flow:

• TIC mode
• Functional mode
• Device Initialization
• DDR initialization
• Enabling DDR access to different processors
• Processor boot sequence
• Processor boot from different memories
• C test Main function
  • Power uncollapse
  • Functional test

7. Coding testcases:

• Listing down test requirements, pass criteria
• Power domains to be up
• clock domains to be up, required frequencies
• Understanding required flow to implement testcase
• knowing library functions to implement above flow
• understanding handshake between Native & SV code

8. Setting up environment:

• Design baseline
  • all design sub component latest baselines
• verif baseline
  • all verif sub component latest baselines
• Updating env for custom baseline

9. Running testcases & regression:

• Command line
• sim_gui mode
• Command line options
• using force files, timing corners, frequency plans

10. Debugging tests:

• tarmac log
• List file
• mpf file
• log
• Wave dump debug
• Message based debug
• Warnings, errors

11. Typical testcase issues:

• Processor not booting
• register looping
• Not working at current frequency plan
• pll not locked
• Memory not preloaded
• clocks not running
• Access is not enabled to register or memory space
• Simulation not proceeding in time
• Simulation is proceeding in time but not completing (looping)
• Interrupt not serviced
• interrupt not generated
• Signal not sampled
• sub module functional issues
• Denali errors
• Memory loading ‘x’ debug
• tied signals, unconnected ports

12. Understanding chip stages:

• RTL code freeze
• Base tapeout
• Metal tapeout
• ECO update
• CS (customer shipment)
• RMA

13. Verification closure:

• Regression 100% pass
• 100% toggle coverage
• reviews high level & low level
• Performance requirements
• Power reqs met

14. Performance requirements?

15. Gate level simulations:

• Significance
• choosing tests for GLS

16. EVCD generation:

• Format?
• Why?
• choosing tests for GLS

17. Vector runs on VT setup

• production vectors
• characterization vectors

18. Generating binaries for running on tester

• Vector debug

19. ECO:

• What stage ECO is issued

20. RMA:

• Significance?

21. Misc:

• SoC Architecture:
• SoC Interconnects
• SoC Digital & Analog Components
• SoC Address Mapping
• SoC Interrupt Mapping
• SoC Frequency Plan
• SoC Performance requirements
• Features
• PLL
• SoC Memories: Msg ram, Iram, DDR, Flash

22. Processor booting from different memories
23. UVC in Testbench setup & sequence usage in SV testcase