RTL Design and Integration training is of 5 months duration focused on enabling participant with RTL integration job role. Training focus will be on RTL coding using Verilog & VHDL, manual integration, developing the glue logic during integration, tool based integration, linting, CDC, UPF, Synthesis and STA.

VLSI Front end domain(Pre-synthesis flow) jobs can be classified in to multiple categories as RTL coding, RTL integration, and Functional verification. VLSI design flow is completely driven by design IP reuse, hence majority of jobs in front end design will be based on RTL integration, which involves integrating multiple IP’s in to SOC as per architecture requirements. RTL integration engineer requires good exposure to RTL coding, Design constraints, Digital design concepts, good coding guidelines and exposure to Synthesis and STA concepts.

Majority of the training institutes are focused on Functional verification training only(with no training on RTL design & integration), which means there are very few trained resources in RTL Design and integration domain, which makes it easy to find a job in front end domain as a RTL integration engineer. Statistics is for every 5 verification engineers, at least one RTL integration engineer will be required.  1000+ students getting trained in Functional verification(across institutes in Bangalore, Hyderabad, Noida, etc), compare this with 10’s of students getting trained in RTL integration. Hence RTL Integration training will give you edge compared to functional verification training.

Like any other job role in VLSI design flow, RTL integration is also a tool intensive job. RTL Integration training will provide the student with expertise on Synopsys Spyglass(Lint and CDC), Design compiler for Synthesis and Primetime for STA. Tools helps with quick turn around in time critical projects, where integration engineer is expected to release the design tag in short timelines. With growing design complexity and reducing timelines, it requires efficient techniques for RTL connectivity and developing the logic for various blocks integration. LINTING is a static analysis of the RTL code based on some set of rules and guidelines. When these rules or guidelines are broken, LINT tool flags errors or warnings, which need to be reviewed, fixed or waived by designer. This course discusses good amount of LINT rules and guidelines, which will enable audience to gain good design practices and perform LINTING if needed.

Course will also focus on Splyglass based CDC(Clock domain crossover) for the synchronisation of various signals moving across one clock domain to another. Course will focus on in-depth analysis of Lint and CDC checks with hands on integration project.

Similar to how we have multiple clocks in a System-On-Chip design we do have multiple power domains being used in modern SOCs for different reasons. Unified Power Format is IEEE standard developed by Accellera. This is used to ease the job of specifying, simulating and verifying the design with multiple power states and power islands. UPF is designed to specify power intent of a design at high level. UPF scripts mention the details of which power rails need to be connected to which IP, whether the register values need to be retained during power off, whether we need an isolation of design in case of power down and manages voltage levels shift as signals cross from one power domain to the other. In this course we discuss the need for multiple power domains, basics of UPF and some examples.

In today’s era, complex SoC chips are being realised using complex VLSI(EDA) tools, of which RTL2GDSII flow is being used extensively during any SoC manufacturing. This has enabled the realisation of very complex digital designs, which starts with design specification and modelling of design using HDL language. This high-level description of the design is mapped to its corresponding hardware using automation, known as “Synthesis,” without which it’s near to impossible to design very complex digital circuits.

Course is offered in 2 modes:

• Full week course (for freshers)
  • 9AM to 1PM on 6 days/week (Friday is break)
  • Institute will be open from 8AM to 9PM on all the days. Student can practice and get mentor support during this time.
• Weekends only course (for working professionals)
  • 9AM to 5:30PM on both Saturday & Sunday
    • Session timings might differ for students from US and other times zones.
  • Dedicated weekday online lab session support(on need basis)

• Multiple trainers each with 15+ years of rich experience of working on complex SOC backend flow in various technology from 45nm to 7nm
• Multiple trainers with exposure to all the industry standard flow starting from Synopsys and Magma

After the successful completion of the course certificate will be issued.