RTL Design and Integration training is of 5 months duration focused on enabling participant with RTL integration job role. Training focus will be on RTL coding using Verilog & VHDL, manual integration, developing the glue logic during integration, tool based integration, linting, CDC, UPF, Synthesis and STA.
VLSI Front end domain(Pre-synthesis flow) jobs can be classified in to multiple categories as RTL coding, RTL integration, and Functional verification. VLSI design flow is completely driven by design IP reuse, hence majority of jobs in front end design will be based on RTL integration, which involves integrating multiple IP’s in to SOC as per architecture requirements. RTL integration engineer requires good exposure to RTL coding, Design constraints, Digital design concepts, good coding guidelines and exposure to Synthesis and STA concepts.
Majority of the training institutes are focused on Functional verification training only(with no training on RTL design & integration), which means there are very few trained resources in RTL Design and integration domain, which makes it easy to find a job in front end domain as a RTL integration engineer. Statistics is for every 5 verification engineers, at least one RTL integration engineer will be required. 1000+ students getting trained in Functional verification(across institutes in Bangalore, Hyderabad, Noida, etc), compare this with 10’s of students getting trained in RTL integration. Hence RTL Integration training will give you edge compared to functional verification training.
Like any other job role in VLSI design flow, RTL integration is also a tool intensive job. RTL Integration training will provide the student with expertise on Synopsys Spyglass(Lint and CDC), Design compiler for Synthesis and Primetime for STA. Tools helps with quick turn around in time critical projects, where integration engineer is expected to release the design tag in short timelines. With growing design complexity and reducing timelines, it requires efficient techniques for RTL connectivity and developing the logic for various blocks integration. LINTING is a static analysis of the RTL code based on some set of rules and guidelines. When these rules or guidelines are broken, LINT tool flags errors or warnings, which need to be reviewed, fixed or waived by designer. This course discusses good amount of LINT rules and guidelines, which will enable audience to gain good design practices and perform LINTING if needed.
Course will also focus on Splyglass based CDC(Clock domain crossover) for the synchronisation of various signals moving across one clock domain to another. Course will focus on in-depth analysis of Lint and CDC checks with hands on integration project.
Similar to how we have multiple clocks in a System-On-Chip design we do have multiple power domains being used in modern SOCs for different reasons. Unified Power Format is IEEE standard developed by Accellera. This is used to ease the job of specifying, simulating and verifying the design with multiple power states and power islands. UPF is designed to specify power intent of a design at high level. UPF scripts mention the details of which power rails need to be connected to which IP, whether the register values need to be retained during power off, whether we need an isolation of design in case of power down and manages voltage levels shift as signals cross from one power domain to the other. In this course we discuss the need for multiple power domains, basics of UPF and some examples.
In today’s era, complex SoC chips are being realised using complex VLSI(EDA) tools, of which RTL2GDSII flow is being used extensively during any SoC manufacturing. This has enabled the realisation of very complex digital designs, which starts with design specification and modelling of design using HDL language. This high-level description of the design is mapped to its corresponding hardware using automation, known as “Synthesis,” without which it’s near to impossible to design very complex digital circuits.
VLSI Design Flow
- RTL coding, lint checks
- RTL integration
- Connectivity checks
- Functional Verification
- Synthesis & STA
- Gate level simulations
- Power aware simulations
- Placement and Routing
- Custom layout
- Post silicon validation
Project management and revision management training
- Revision Management
- Project Management
- Detailed overview of project phases
- Significance of RTL integration in VLSI Design Flow
Advanced Digital Design
- Digital Design basics
- Combinational logic
- Sequential logic, FF, latch, counters
- Setup time, Hold time, timing closure, fixing setup time and hold time violations
- STA basic concepts time, Hold time, timing closure, fixing setup time and hold time violations
- File and directory management
- User administration
- Environment variables
- Commonly used commands
- Shell scripting basics
- SEd and AWK
- Revision management
- Introduce TCL
- Why TCL?
- TCL Script Processing
- Understand TCL uses and strengths
- Writing simple TCL scripts
- TCL for VLSI scripting
- TCL : Main Features
- TCL in EDA
- TCL shell (tclsh)
- Working with TCL scripts (UNIX)
- TCL Interpreter in SoC Design Tools
- TCL Scripting for SoC Design
- TCL Commands
- Substitution and Command Evaluation
- Mathematical Functions
- Control flow : if, if-else, switch, for, foreach, while, break and continue
- string, string operations
- List, List manipulation
- Arrays, array methods
- Working with files
- Command line arguments
- Regular expressions
- Complete TCL Scripts
- TCL Packages
- Detailed overview of all Verilog-2001 constructs
- Multiple hands on projects
- Pattern detector
- Synchronous and Asynchronous FIFO
- Interrupt controller
- SPI Controller
- Watchdog timer
- PISO and SIPO
- Vending machine
- Overview of RTL Integration
- Manual RTL integration
- Need for Tool based Integration
- coreTools Basics
- Usage model for IP packaging
Usage model for IP integration
- Purpose of LINTING
- SpyGlass Lint Tool Flow
- Rules in SpyGlass Lint
Power Aware Design Techniques
- Introduction to Low Power
- Power Intent and UPF
- Special low power cells and requirements.
- Introduction to SpyGlass LP Static Check
- Introduction to Synthesis
- Data Setup for DC
- Accessing Design and Library Objects
- Constraints: Reg-to-Reg and I/O Timing
- Constraints: Input Transition and Output Loading
- Constraints: Multiple Clocks and Exceptions
- Constraints: Complex Design Considerations
- Post-Synthesis Output Data
Logic Equivalence Checks (LEC)
- Basic concepts of Formal verification and LEC
- Input generation for LEC
- Hands on project
Hands on projects
- 2 Hands on projects based on complete RTL integration flow, CDC, Lint, Synthesis and STA
Course is offered in 2 modes:
- Full week course (for freshers)
- 9AM to 1PM on 6 days/week (Friday is break)
- Institute will be open from 8AM to 9PM on all the days. Student can practice and get mentor support during this time.
- Weekends only course (for working professionals)
- 9AM to 5:30PM on both Saturday & Sunday
- Session timings might differ for students from US and other times zones.
- Dedicated weekday online lab session support(on need basis)
||RTL Design and Integration Training
||5 months training
|Entrance Test Syllabus
||1. Digital Electronics 2. CMOS 3. ASIC flow
|Registration & Course commencement date
||Full week course
||Saturday & Sunday(8:30AM – 4:30PM India time. Monday to Friday(9:30AM to 12:30PM).
||Weekdays sessions will be focused on training on Verilog labs, Digital Design, Linux and TCL scripting.
||Saturday & Sunday(8:30AM – 4:30PM India time. Flexible timings for students attending online from US)
||8:30AM – 12:30PM (Theory session offered by trainer)
||1PM – 4:30PM (Lab & tool based session guided by mentor). Students from US will get support in different time.
||Students will take the weekday tests and assignments from home.
||Students also get support on complete project flow during weekdays as well.
|New batch starts
||Every 6 Weeks
||INR 39000 (All inclusive) (Classroom training)
INR 49000 (All inclusive) (Online training)
||Synopsys Splyglass, Design compiler, Primetime
|Mode of training
||Classroom training at Institute
||Online training using live training sessions
||Tool access for 12 months at the institute
||Issued based on 50% assignment completion as criteria
||20(evaluation test followed by discussion on same).
||Job opportunity in at least 6 companies. Further job Support till students gets job.
||15+ Years of industrial experience
Do you offer support after course completion?
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
What are the Course Prerequisites?
- Digital design fundamentals
- Verilog coding basics
What if I miss few sessions during course?
- Each session of course is recorded, missed session videos will be shared
Course has started few weeks back, can I still join the course in between?
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
After the successful completion of the course certificate will be issued.