Physical Verification Training
Physical Verification training is a four months course targeted for experienced engineers, BTech, BE, MTech, ME and diploma graduates planning to make career as a Physical verification engineer. Physical Verification course ensures that a fresher/experienced engineer is prepared on all the aspects of Physical Verification including DRCs, LVS, ERC, Antenna Checks, Latchup, Exposure to the Importance of reliability checks like EM and IR analysis Design for manufacturability (DFM)checks, Electrostatic discharge (ESD) path checks.
Course will consist of 70% exposure to hands on projects and 30% theory sessions.
Course includes training on ASIC flow, Advanced Digital Design concepts, CMOS basics, FinFET basics, various memory architectures, Standard cell, IO’s and Analog layout techniques. Course also includes training on UNIX, revision management, scripting and soft skill for effective interview performance.
Course includes 20+ detailed labs & assignments covering all aspects of Physical Verification with multiple hands on projects.
Course starts with detailed sessions on semiconductors, Ohms law, Kirchhoff law’s, Diode-operation, CMOS operations, second order effects, FinFET’s, and detailed fabrication process, which is followed by assignments and hands on projects.
Course will also include detailed sessions on layout basics, hands on standard cell layouts, IO layout and memory layout for different architectures with detailed physical verification checks for the same.