Online VLSI Training
Online VLSI Training
VLSI Online Training in Functional Verification (VG-VTO) is a 19 weeks course structured to enable engineers develop skills in full breadth of SystemVerilog, UVM & OVM features in complex testbench development. VLSI Training course is targeted for verification engineers with with Verilog based functional verification exposure and want to gain expertise in SystemVerilog, UVM & OVM based verification. Every aspect of course is supported with detailed examples to enable easier & quicker understanding. Course also covers multiple industry standard projects based on AXI, AHB and Memory Controller. All projects are executed from scratch. Lab sessions are planned at regular intervals to enable student work on these projects from scratch with trainer guidance. Below is quick overview of what is covered as part of VG-VTO.
- Systemverilog Training, UVM Training
- AXI3.0 Protocol, AXI VIP Development
- Memory Controller Functional Verification
- UVM & OVM Language Constructs with with detailed examples
- AHB Protocol, AHB UVC development & AHB I/C functional verification
- Register layer development for USB2.0
SystemVerilog for Advanced Verification
- Classes : Object Oriented Programming
- Arrays, Data Types, Literals, Operators
- Scheduling Semantics, Inter process Synchronization
- Processes, Threads, Tasks and Functions
- Randomization, Constraints
- Interface, Clocking blocks, Program Block
- Functional Coverage
- Assertion Based Verification
- System Tasks & Functions
- Compiler Directives
- DPI
ASIC Verification Concepts
- SoC Verification Concepts
- Module Level Verification
- Constrained Random Verification
- Coverage Driven Verification
- Directed Verification
- Assertion Based Verification
Verification IP Development
- AXI Protocol Concepts : Features, Signals, Timing Diagrams
- AXI VIP Architecture Development
- VIP Component Coding
- AXI Slave model testcase development
- Testcase debugging
Module(IP) Level Verification Project
- Projects executed: Memory Controller (or) Ethernet MAC (or) DMA Controller (or) AXI2OCP Bridge (or) AXI2AHB Bridge (or) AHB2APB (or) USB Core (or) AXI Interconnect (or) AHB Interconnect (or) a project of similar complexity
- Specification analysis
- Verification Plan creation
- Feature & Scenario Listing down
- TB architecture creation
- Building Top level verification environment
- TB component coding and integration
- Sanity test case and environment bring up
- Complete test case coding
- Building regression test suite
- Functional coverage and code coverage analysis
Verification Methodologies: UVM & OVM
- AHB Interconnect verifiation project used as reference design to learn UVM & OVM
- AHB Interconnect will be verified from scratch while teaching all aspects of UVM
- UVM/OVM TB Architecture
- UVM Class Library, Macros, Utilities
- UVM Factory, Synchronization, Containers, Policies
- UVM Components, Comparators, Sequences, Sequencers
- Stimulus Modeling, Sequences & Sequencers
- Creating UVCs and Environment
- Simulation Phases
- TLM Overview, Components
- Configuring TB Environment
- Register Layer, Configuration DB & Resource DB
- Connecting multiple UVCs
- Creating TB infrastructure
AHB UVC Development
- AHB Protocol : Features, Signals, Timing Diagrams
- AHB UVC Architecture
- AHB UVC Component Coding
- AHB UVC Seqeunce & Test Development
AHB Interconnect Functional Verification
- AHB Interconnect Testbench Architecture
- AHB UVC & APB UVC in Interconnect Testbench setup
- Verification Component Coding
- Testcase & virtual sequence Development & Debug
- Sanity test case and environment bring up
- Testcase & Sequence coding
- Building regression test suite
- Functional coverage and code coverage analysis
Course Assignments
- VIP Developmet for one of OCP/Wishbone/APB/Ethernet Protocols
- Verification of PCIEx Physical Layer LTSSM FSM from scrach
- Functional Verifcation of a complex module
- UVC Development for AXI Protocol
- PCIe LTSSM FSM Verification
- Register Model Development for SPI Core
Course | VLSI Front End Training for Experienced Engineers |
---|---|
Duration | 19 weeks |
Schedule | Both Saturday & Sunday(8:30AM – 4:00PM India time) |
8:30AM – 12PM (Trainer led theory and lab sessions) | |
1PM to 4PM (Mentor guided lab & assignment solving sessions) | |
New batch starts | every 7 weeks |
Fee | INR 38000 (Online Training) |
Tool | Questasim |
Mode of training | Classroom training at Institute |
Online training using live training sessions | |
Certificate | Issued based on 50% assignment completion as criteria |
Admission criteria | Student need to undergo evaluation test based on Verilog Digital Design VLSI Technology and Aptitude |
Assignments | 40 |
Trainer | 12+ Years exp in RTL design & Functional verification |
After completing this training, you will know how to:
- Utilisation of the primary 7 series FPGA architecture resources
- Project Manager to start a new project
- Identify the available Vivado IDE design flows (project based and non-project batch)
- Identify file sets (HDL, XDC, simulation)
- Analyse designs by using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer.
- Synthesize and implement an HDL design
- Utilise the available synthesis and implementation reports to analyse a design (utilisation, timing, power, etc.)
- Build custom IP with the IP Library utility
- Make basic timing constraints
- Describe and analyse common STA reports
- Identify synchronous design techniques
- Describe how an FPGA is configured
PROJECTS & LABS
- Lab 1: Vivado IDE – create a simple HDL design and simulate the design using the HDL simulator available in Vivado design suite. Generate the bit stream and debug the design using Vivado Logic Analyzer.
- FPGA simulation and generating the bit stream of combinational and sequential circuits, memories, and registers through the Vivado IDE
- FPGA design of Synchronous and Asynchronous FIFO.
- FPGA design of a I2C protocol
- FPGA design of a SPI protocol
- Lab2:Vivado IP integrator. Vivado project and use IP Integrator to develop a basic embedded system for a target board.Extending the Embedded System into Programmable Logic
- a. Adding Peripherals in Programmable Logic. Extend the hardware system by adding AXI peripherals from the IP catalog. Adding Your Own IP Peripheral
- Lab 3: Creating and Adding Your Own Custom IP.Use the Manage IP feature of Vivado to create a custom IP and extend the system with the custom peripheral.
- Lab 4: Software Development Environment. Writing Basic Software Applications. Write a basic C application to access the peripherals.
- Lab 5: Software Development and Debugging Software Debugging Using SDK.Use API to drive CPU’s timer. Perform software debugging using SDK.
- Lab 6: Debugging using Chip scope-Vivado Logic Analyzer cores insert various Vivado Logic Analyzer cores to debug/analyze system behavior.
- Lab7.Software Application Discussion about the Possible Applications using Zynq AP SOC
- Lab 8.Installing and running Linux. Installing Petalinux and Booting
Board used in the course
- ZYNQ Processor
- 667 MHz dual-core Cortex-A9 processor
- DDR3L memory controller with 8 DMA channels and 4 High Performance AXI3 Slave ports
- High-bandwidth peripheral controllers: 1G Ethernet, USB 2.0, SDIO
- Low-bandwidth peripheral controllers: SPI, UART, CAN, I2C
- Programmable from JTAG, Quad-SPI flash, and microSD card
- Programmable logic equivalent to Artix-7 FPGA
- Memory
- 1 GB DDR3L with 32-bit bus @ 1066 MHz
- 16 MB Quad-SPI Flash with factory programmed 128-bit random number and 48-bit globally unique EUI-48/64™ compatible identifier
- microSD slot
- Power
- Powered from USB or any 5V external power source
- USB and Ethernet
- Gigabit Ethernet PHY
- USB-JTAG Programming circuitry
- USB-UART bridge
- USB 2.0 OTG PHY with host and device support
- Audio and Video
- Pcam camera connector with MIPI CSI-2 support
- HDMI sink port (input) with CEC (Zybo Z7-20) and without CEC (Zybo Z7-10)
- HDMI source port (output) with CEC
- Audio codec with stereo headphone, stereo line-in, and microphone jacks
- Switches, Push-buttons, and LEDs
- 6 push-buttons (2 processor connected)
- 4 slide switches
- 5 LEDs (1 processor connected)
- 2 RGB LEDs (Zybo Z7-20) and 1 RGB LED (Zybo Z7-10)
- Expansion Connectors
- 6 Pmod ports (Zybo Z7-20) and 5 Pmod Ports (Zybo Z7-10)
- 8 Total Processor I/O
- 40 Total FPGA I/O (Zybo Z7-20) and 32 (Zybo Z7-10)
- 4 Analog capable 0-1.0V differential pairs to XADC
- 6 Pmod ports (Zybo Z7-20) and 5 Pmod Ports (Zybo Z7-10)
Zynq FPGA finds extensive applications in the following.
- Automotive applications
- Computer architecture
- Embedded Linux OS development
- Embedded processing systems
- Hardware/software co-design.
- Build and include hardware accelerators to meet bandwidth demanding applications
What are the Course Prerequisites?
- Expertise on Verilog
- Exposure to Testbench component coding using Verilog
Does course cover practical sessions on SystemVerilog usage?
- Each aspect of course is supported by lot of practical examples
- Ethernet loopback design used as reference design from Session#1 towards implementing and learning SystemVerilog constructs
- All SystemVerilog course examples, AXI VIP, and Memory Controller Verification environment implemented from scratch as part of sessions
- Dedicated full day lab sessions to ensure student does complete testbench development from scratch
Is it possible to cover so many things in 8 weeks?
- We have done it for 23 Batches so far, next batch is no exception
- Course requires student to spend at least 6+ hours of time a week to revise the concepts
What if I miss few sessions during course?
Each session of course is recorded, missed session videos will be shared
Course has started few weeks back, can I still join the course in between?
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
Do you offer support after course completion?
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
Trainer Profile
- 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
- Experience of working on multiple complex module level projects
After the successful completion of the course certificate will be issued.