Online Verilog Training
VLSI Design and Verification training for Freshers
Overview
Online training in Verilog for Design & Verification (VG-VO) is a 7 weeks training focused on following aspects.
- Verilog-2001 language constructs
- Implementation of standard designs and testbench using Verilog
- Course content & schedule is same as classroom Verilog training
Syllabus
Introduction to Verilog
- Introduction to Verilog Course
- Module
- Data types
- Data Flow
- Procedural Blocks
- Language Statements
- State Machines
- Gate Level Implementation
- Verilog Programing Interface(& PLI)
Commonly asked Verilog Design Examples : All covered in course training
- Flipflop (Synchronous & Asynch Reset), Latch
- Counter-Gray code counter, modulo, ring, johnson, up counter, down counter
- Shift register implementation
- Half adder, full adder, multiplexer
- Dual port memory write, read design & testbench
- encoder, decoder, various gates
- Primitive implementation using table, endtable
- Pattern detector
- Coin counter for tea vending machine
- Traffic light controller(TLC)
- CRC generation code
- Watchdog timer implementation
- Synchronous FIFO
- Asynchronous FIFO
- Memory implementation
- example to showcase race condition using blocking assignments
- system task usage: $display, $monitor, $strobe
- PLI, VPI implementation
- Memory controller RTL understanding, architecture understanding
- Clock generation with Duty cycle & Jitter
- PCIe different layer implementation
- Interrupt Controller
Verilog for Verification
Verification of all above designs using Verilog
Schedule & fee
| Course | Verilog for Design & Functional Verification |
|---|---|
| Duration | 7 weeks |
| Schedule | ||
| Freshers | Full week course | |
| Saturday & Sunday(8:30AM – 4:30PM India time. Monday to Friday(9:30AM to 12:30PM). Flexible lab sessions for US Students. | ||
| Weekdays sessions will be focused on Digital design, course labs, assignments solving and interview focused sessions. | ||
| Students also get support on complete project flow during weekdays as well. | ||
| New batch starts | Every 7 Weeks | |
| Fee | INR 9000 | |
| Tool | Questasim | |
| Mode of training | Classroom training at VLSIGuru Institute(Horamavu) | |
| Online training using live training sessions | ||
| Certificate | Issued based on 50% assignment completion as criteria | |
| Batch Size | 20 | |
| Assignments | 24 | |
| Trainer | 12+ Years exp in RTL design & Functional verification |
Faqs
What are the Course Prerequisites?
Expertise on design design concepts
Does course cover practical sessions on UVM usage?
- Each aspect of course is supported by lot of practical examples
- Dedicated full day lab sessions to ensure student does complete testbench development from scratch
Course has started few weeks back, can I still join the course in between?
You will have option to repeat the course any time in next 1 year
Do you offer support after course completion?
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
Audience
Target Audience:
- MTech & BTech freshers would like to start learning directed verification
- Engineers with prior experience in other domains of VLSI or experience non-VLSI domains, want to make career in Functional Verification
- Engineering college faculty looking to enhance their VLSI skill set
Trainer
- Multiple trainers with 10 years of average experience of working in Functional Verification domain across mobile, networking, high speed peripheral domains.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Subsystems
- Experience of working on multiple complex module level projects
Course Certificate
After the successful completion of the course certificate will be issued.