Online UVM Training
UVM & OVM For Functional Verification
Overview
Online training in UVM & OVM for Functional Verification (VT-VMO) is structured to enable engineers develop their skills in full breadth of UVM & OVM features in complex testbench development. VT-VMO course is targeted for verification engineers who are proficient with SV based functional verification and are looking to explore UVM & OVM based verification. Course has been framed in a way to make UVM & OVM learning a fun and interesting activity. Every aspect of course is supported with multiple examples to enable easier & quicker understanding. Course also covers multiple industry standard projects, all of these executed from scratch. Lab sessions are planned at regular intervals to enable student work on these projects from scratch with trainer guidance. Below is quick overview of what is covered as part of VT-VMO.
- UVM & OVM Base class and Macro usage with detailed examples on each construct usage
- AHB Protocol, AHB UVC development & AHB I/C functional verification
- Register layer development for USB2.0
- USB2.0 Core Functional verification
Syllabus
Verification Methodologies: UVM & OVM
- AHB Interconnect verifiation project used as reference design to learn UVM & OVM
- AHB Interconnect will be verified from scratch while teaching all aspects of UVM
- UVM/OVM TB Architecture
- UVM Class Library, Macros, Utilities
- UVM Factory, Synchronization, Containers, Policies
- UVM Components, Comparators, Sequences, Sequencers
- Stimulus Modeling, Sequences & Sequencers
- Creating UVCs and Environment
- Simulation Phases
- TLM Overview, Components
- Configuring TB Environment
- Register Layer, Configuration DB & Resource DB
- Connecting multiple UVCs
- Creating TB infrastructure
AHB UVC Development
- AHB Protocol : Features, Signals, Timing Diagrams
- AHB UVC Architecture
- AHB UVC Component Coding
- AHB UVC Seqeunce & Test Development
AHB Interconnect Functional Verification
- AHB Interconnect Testbench Architecture
- AHB UVC & APB UVC in Interconnect Testbench setup
- Verification Component Coding
- Testcase & virtual sequence Development & Debug
USB2.0 Register Layer
- Listing down registers
- Creating Register Model
- Integrating Register Model in to Testbench
- Using Register Model to create tests
- Using Register Model in scoreboard
USB20 Core Functional Verification
- Specification Reading, Feature Listing, Scenario Listing
- TB architecture creation
- Building Top level verification environment
- TB component coding and integration
- Sanity test case and environment bring up
- Testcase & Sequence coding
- Building regression test suite
- Functional coverage and code coverage analysis
Course Assignments
- UVC Development for AXI Protocol
- PCIe LTSSM FSM Verification
- Register Model Development for SPI Core
Schedule & fee
| Course | UVM Training in Functional Verification |
|---|---|
| Duration | 7 weeks |
| Schedule | Both Saturday & Sunday (9AM – 5PM IST) |
| 9AM to 1PM (Trainer led sessions covering theory and labs) | |
| 1:45PM to 5PM (Mentor guided sessions covering labs assignments and doubt clarifications). Online students from US will get support in different time. | |
| Course repeats | Every 10 Weeks |
| Fee | INR 16000 (all inclusive) |
| Tool | Questasim & VCS |
| Online training using live training sessions | |
| Certificate | Issued based on 50% assignment completion as criteria |
| Batch Size | 20 |
| Assignments | 20 |
| Admission criteria | Student need to undergo evaluation test based on verilog & SV |
| Placement support | Interview opportunity in at least 6 companies |
| and scoring good grade in monthly evaluation test | |
| Trainer | 12+ Years exp in RTL design & Functional verification |
Faqs
What are the Course Prerequisites?
- Expertise on SystemVerilog Language
- Exposure to Testbench component coding using SystemVerilog
Does course cover practical sessions on UVM usage?
- Each aspect of course is supported by lot of practical examples
- AHB Interconnect is reference design from Session#1 towards implementing and learning different UVM aspects
- All UVM course examples, AHB UVC, AHB Interconnect and USB2.0 Core Verification environment implemented from scratch as part of sessions
- Dedicated full day lab sessions to ensure student does complete testbench development from scratch
Is it possible to cover so many things in 9 weeks?
- We have done it for 23 Batches so far, next batch is no exception
- Course requires student to spend at least 6+ hours of time a week to revise the concepts
What if I miss few sessions during course?
Each session of course is recorded, missed session videos will be shared
Course has started few weeks back, can I still join the course in between?
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
Do you offer support after course completion?
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
Audience
Target Audience:
- Verification engineers looking to learn advanced verification techniques
- MTech & BTech freshers who are well versed with SV, and would like to learn advanced verification
- Engineers with prior experience in other domains of VLSI or experience non-VLSI domains, want to make career in Functional Verification
- Engineering college faculty looking to enhance their VLSI skill set
Trainer
Trainer Profile
- 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
- Experience of working on multiple complex module level projects
Course Certificate
After the successful completion of the course certificate will be issued.