MTech VLSI Intership
VHDL Training with Hands on labs
- 5 weeks training
- 8 hours per week (2 sessions on Saturday & Sunday, 4 Hours each)
- Fee: 5,000
- Next Batch: Adhoc
- VHDL language constructs (2 days)
- Design RTL Coding project (1 day)
- 12+ year’s exp. in functional verification with exposure to multiple SOC, Subsystem and module level verification projects.
- VHDL Language constructs
- Fundamental VHDL units
- Library Declaration
- Entity Declaration
- Architecture Declaration
- Data types
- Basic TextIO
- Primitive programming
- Data flow programing
- Signals & Variables, State machines
- Memory Designing
- Structural programming
- Function & Procedure
- Hierarchical Designs
- Parameterized Design entities
- Procedural Testbenches
- VHDL Synthesis
- VHDL Lint and Debug
- Labs based on simple design examples like FIFO, Dual port RAM, FSM’s, etc
- DMA Controller Design using VHDL
- Test to assess student learning at the end of course
- Individual session notes
- Lab files, including example solutions that illustrate proper and efficient coding styles
Given the competition in VLSI job market, it becomes essential for ME & BE students to get themselves prepared for VLSI job while they are in college.
Below is how internship would help:
- Helps bridge the gap between graduate academics with industry requirements.
- Saves 6 months time spent on training after passing out from college.
- Helps them choose right project of ME.
- 1 year experience and internship certificate
MTech projects are based on industry standard design & verification projects MTech internship will be targeted towards enabling student learn complete verification concepts including SV & UVM based verification.
- Projects on IEEE standard and based design & verification using SV & UVM
- Projects based on industry standard Protocols like AXI, AHB, USB, PCIe etc
Schedule & fee