MTech VLSI Intership
VHDL Training with Hands on labs
Schedule:
- 5 weeks training
- 8 hours per week (2 sessions on Saturday & Sunday, 4 Hours each)
- Fee: 5,000
- Next Batch: Adhoc
Agenda:
- VHDL language constructs (2 days)
- Design RTL Coding project (1 day)
Trainer Profile
- 12+ year’s exp. in functional verification with exposure to multiple SOC, Subsystem and module level verification projects.
Course Content:
- VHDL Language constructs
- Fundamental VHDL units
- Library Declaration
- Entity Declaration
- Architecture Declaration
- Data types
- Basic TextIO
- Primitive programming
- Data flow programing
- Signals & Variables, State machines
- Memory Designing
- Structural programming
- Function & Procedure
- Hierarchical Designs
- Parameterized Design entities
- Procedural Testbenches
- VHDL Synthesis
- VHDL Lint and Debug
- Labs based on simple design examples like FIFO, Dual port RAM, FSM’s, etc
- DMA Controller Design using VHDL
Trainee Assessment:
- Test to assess student learning at the end of course
Course Material:
- Individual session notes
- Lab files, including example solutions that illustrate proper and efficient coding styles
Given the competition in VLSI job market, it becomes essential for ME & BE students to get themselves prepared for VLSI job while they are in college.
Below is how internship would help:
- Helps bridge the gap between graduate academics with industry requirements.
- Saves 6 months time spent on training after passing out from college.
- Helps them choose right project of ME.
- 1 year experience and internship certificate
MTech projects are based on industry standard design & verification projects MTech internship will be targeted towards enabling student learn complete verification concepts including SV & UVM based verification.
- Projects on IEEE standard and based design & verification using SV & UVM
- Projects based on industry standard Protocols like AXI, AHB, USB, PCIe etc
Course divided in to 2 aspects Learning phase Application phase During ‘learning phase’; Student will undergo 3 months extensive training on Advanced Digital Design, Verilog, SystemVerilog and UVM basics, standard protocols like AXI, AHB, Ethernet MAC, etc. Student will be working on multiple industry standard project as part of SV & UVM learning. During ‘application phase’, Student will be working on industry standard project with trainer guidance. Same project can be used as MTech Project. Project done as part Internship learning phase: Ethernet Loopback Design Functional Verification AXI VIP Development Memory Controller Design Functional Verification AHB UVC Development Projects as part of Internship application phase, student can choose one of projects AXI2OCP Bridge Design Functional Verification Ethernet MAC Design Functional Verification AXI Interconnect Design Functional Verification AHB Interconnect Design Functional Verification AHB2AXI Bridge Design Functional Verification UART Controller Design Functional Verification PRCM Design Functional Verification DMA Controller Design Functional Verification Detailed Course Content: Advanced Digital & Analog design concepts Verilog
- Internship Duration: 1 year
- Fee : INR 16,000 excluding UVM essentials
- INR 20,000 including UVM essentials
- Tools : Questasim(Mentor Graphics)
- Access to tool using remote connection
- Certificate of course completion and experience letter
How internship helps?
- Targeted to bridge gap in academics to industry
- Exposure to Verilog, SystemVerilog and UVM including multiple industry standard projects
What are the Course Prerequisites?
- Expertise on verilog Language
- Exposure to Testbench component coding using verilog
Course has started few weeks back, can I still join the course in between?
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
Do you offer support after course completion?
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
Trainer Profile
- 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
- Experience of working on multiple complex module level projects
After the successful completion of the course certificate will be issued.