MTech VLSI Intership

VHDL Training with Hands on labs

Schedule:

    • 5 weeks training
    • 8 hours per week (2 sessions on Saturday & Sunday, 4 Hours each)
    • Fee: 5,000
    • Next Batch: Adhoc

Agenda:

  • VHDL language constructs (2 days)
  • Design RTL Coding project (1 day)

 

Trainer Profile

  • 12+ year’s exp. in functional verification with exposure to multiple SOC, Subsystem and module level verification projects.

 

Course Content:

  • VHDL Language constructs 
    • Fundamental VHDL units
    • Library Declaration
    • Entity Declaration
    • Architecture Declaration
    • Data types
    • Basic TextIO
    • Primitive programming
    • Data flow programing
    • Signals & Variables, State machines
    • Memory Designing
    • Structural programming
    • Function & Procedure
    • Hierarchical Designs
    • Parameterized Design entities
    • Procedural Testbenches
    • VHDL Synthesis
    • VHDL Lint and Debug
  • Labs based on simple design examples like FIFO, Dual port RAM, FSM’s, etc
  • DMA Controller Design using VHDL

 

Trainee Assessment:

  • Test to assess student learning at the end of course

Course Material:

  • Individual session notes
  • Lab files, including example solutions that illustrate proper and efficient coding styles
After the successful completion of the course certificate will be issued.