LEARNING DIGITAL DESIGN
Learning Digital Design
Digital Design & Analog Design
- All components that go in to an SOC can be divided in to either digital or analog
- All these components involve various digital and analog design concepts starting CMOS, gates, delays, latch, flip flop, etc to name a few
- As a fresher it is essential to know all these concepts for multiple reasons
- o Learning above concepts, makes it easy to understand advanced concepts as you move to learn protocols like PCIe, USB, DDR, AXI, etc
- o Majority of interviews focus on Digital design & Verilog coding concepts
- o There are few domains of VLSI like Physical design, STA, GLS which only require strong digital design understanding.
- Even though we don’t use Analog design concepts much in VLSI functional verification, however it need to be learnt with an eye on interviews.
What to learn
- Digital Design learning, please note it is not limited to it.
- Flipflop FF implementation using NAND gates Setup time, hold time definition and calculation Metastability
- Latch
- Counter gray counter ring counter mod counter johnson counter
- FIFO, how is it used for data flow synchronization, Synchronous FIFO Asynchronous FIFO How handshaking can replace FIFO
- Race condition
- Multiplexer Using MUX to create different logic gates
- Decoder, encoder, priority decoder
- even, odd parity, CRC : How these are useful in detecting transmission errors
- Master-slave handshaking
- CMOS, PMOS, NMOS
- Inverter using CMOS
- Half adder, full adder using half adder
- truth table for half adder, full adder, multiplexer, counters above
- buffer usage in digital design, signal drive strength, load, significance
- PLL, VCO, how clock is generated in real SOC, we don’t use forever logic, we use PLL
- Generating one clock frequency from exisitng clock Use 100MHz clock to generate 200Mhz Use 100Mhz clock to generate 50MHz
- T-Flipflop, use in 2 & 3 stage synchronizers
- Clock domain crossing, use of synchornizers
- Reset, Asynchronous reset, synchronous reset
- Moore & Mealy state machine
- Signed, unsigned numbers, 1’s complement, 2’s complement
- Karnaugh map, using truth table
- Octal, hexa, decimal, binary conversions
- NAND gate or NOR gate as universal gate
- Memory, different types of memroies
- rise, fall time, propagration delay, SDF format
- setup time, hold time calculation for flipflop
- Fundamentals of STA, PD, Layout, DFT, Post Silicon Validation
- Basics of Analog circuits, Oscillator, ADC, DAC
- SDF Annotation, GLS concepts
- Clock routing using T-branching : keeping all path length same
- Clock routing using Diasy-chain routing
- Clock duty cycle and clock jitter Generating clock with 60% duty cycle