RTL simulations is the basic requirement to signoff design cycle, but lately there is an increasing trend in the industry to run gate level simulations (GLS) before going into the last stage of chip manufacturing. Improvements in static verification tools like Static timing analysis (STA) and Equivalence Checking (EC) have leveraged GLS to some extent but so far none of the tools have been able to completely remove it. GLS still remains a significant step of the verification cycle footprint.

There is lot of motivation for running GLS even while STA is leveraging timing checks to major extent. GLS Training(VG-GLS) course will focus on teaching all the aspects of GLS from setup, test plan, frequency plans, SDF corners, and non-timing simulations. Course will also focus on various issues faced during GLS and debugging those. Course will involve hands on GLS project using complex gate level netlist.

GLS Training(VG-GLS) Schedule

• Duration:  3 weeks
• Fee : INR 5,000
• Certificate of course completion

Trainer Profile

• 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
• Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
• Experience of working on multiple complex module level projects

After the successful completion of the course certificate will be issued.