FREQUENTLY ASKED QUESTIONS
- Industry focused training at affordable fee
- Trainers with 10+ years of exp, currently working in industry.
- Projects based on industry standard protocols like AXI, AHB, USB, PCIe, DDR, etc
- All projects executed from scratch
- Dedicated lab sessions to ensure student develops complete project from scratch
- Only Institute to offer training in all aspects of VLSI Design flow
VLSI Flow can be majorly be divided in to 11 steps as below. These can be majorly divided in to two categories, VLSI Front end flow and VLSI Back end flow. VLSI Front end flow consists of design flow starting from architecture to functional verification. Rest of the flow starting from Synthesis to Physical verification is VLSI Back end flow. Assuming team has 50 engineers.
Below shows possible distribution of team members in various domains(value in brackets is number of engineers)
– RTL Design (2, SOC development mostly works on IP reuse, most of IP development happens out side India)
– RTL Integration (2)
– Functional verification (13)
– Formal verification (1)
– Power aware verification (1)
– Synthesis (2)
– Physical Design (13)
– STA (3)
– DFT (2)
– Custom Layout (4)
– Physical Verification (4)
– Post Silicon validation (3)
VLSI Design flow starts with requirments, then it gets developed as a architecture, which is implemented using Verilog RTL(or VHDL) coding. This RTL code is verified using Systemverilog & UVM (C + SV for SOC) based testbenches. This stage is called functional verification. The flow till this stage is called as VLSI Front end flow(similar to software job). This is more programming oriented. The flow starting from this point(RTL code) till it gets manufactured in to a chip is called VLSI Backend flow. It involves multiple stages(Synthesis, DFT, Physical Design, STA, Custom Layout, Physical Verification, Fabrication and Post Silicon validation). VLSI Front end domain is more programming oriented and VLSI Back end is more tool and VLSI technology oriented. As shown above, every domain offers job opportunities. Even though Functional verification and Physical design offers more opportunities, they also have more people undergoing training. Hence student should choose domain of training based on interest rather than job openings.
RTL Design, RTL integration, Functional verification, formal verification is more focused on understanding design specification, learning bus protocols and implementing designs and testbenches based on these protocols using Verilog, SV & UVM. Job role is more programming oriented.
Rest of the flow(from Synthesis toll Post silicon validation), also called post-synthesis flow does not involve much of programming. These jobs are more EDA tool usage oriented. Engineer need to learn various aspects of the flow and learn required commands in tool to implement these steps. It may involve learning 100’s of tool commands and their significance to the VLSI implementation flow. The overall flow is implemented using TCL commands(above tool commands), so it will TCL exposure. It also requires good fundamentals of CMOS, FinFET, 2nd order effects, timing closure and digital design.
Student doesn’t need to learn all the aspects of VLSI flow. Choose one domain and get complete expertise in that topic.
When a student joins institute, we do not make any assumption on their current preparation level, all the training starts from basics.
Education should be affordable to majority of the people. Institute is driven by the ideology of making quality education affordable to everyone. Having said that, all courses are well organized and with industry best trainers covering each course.
All the jobs in VLSI industry at 0 – 7 year experience level does not require expertise in complete VLSI flow. The engineer is not expected to work on complete flow during initial 0-7 years of experience. Focus on complete flow does more harm than helping engineer’s career, with reduced focus on a specific aspect.
Job require specialization in one of the aspect below, and jobs can be categorized as below :
- Marketing team
- Design Engineer
- Integration & Synthesis Engineer
- Verification Engineer (Functional & Timing Verification)
- PD Engineer
- STA Engineer
- Layout Engineer
- DFT Engineer
A job aspirant should focus on one of above aspects to get in to the industry, while gaining more expertise on the chosen aspect by extensive focus, rather than doing course on complete flow .
Institute has tie up with select VLSI companies. Student will get opportunity to attend these companies interviews.
Number of opportunities student gets also depends on their performance during course.
No. As a Design & Functional Verification engineer, there is essentially no difference between ASIC & FPGA. Both ASIC & FPGA have same flow during design & verification. The difference comes in way backend flow is done, which does not affect a verification engineer.
The reason colleges/universities focus on teaching design in FPGA flow is because of the low cost of project execution on FPGA. Executing a project on FPGA involves only Spartan or any other FPGA board. Whereas same design flow costs in millions of rupees to be executed in ASIC flow. Hence colleges focus on FPGA flow teaching.
- Each Session of course is recorded. Student will be provided with option to view the recorded videos.
- Student also has option to repeat complete course at no additional fee. Only for classroom students.
Yes. All the participants will receive VLSI Training completion certificate from VLSIGuru, with their grades based on their performance during the VLSI training.
Tools from Synopsys and Mentor Graphics. We are the only training institute to have licenses from both Synopsys and Mentor graphics.
It depends on current preparation level. Below is the time it takes to gain perfection in various courses. Verilog : 105 Hours Systemverilog: 240 Hours UVM: 150 Hours Physical Design Flow: 360 Hours CMOS + FinFET + Digital Design : 80 Hours PERL or TCL Scripting: 30 Hours UNIX : 15 Hours VLSI Design flow: 10 Hours Digital Design(Basic & Advanced): 50 Hours Fresher looking for job in VLSI Front end or Back end will require 600 hours in total. Duration of preparation will depend on number of hours(focused preparation time) spent per day. For each hour of training, student need to spend 2 hours of time for self-preparation 1 Hour for revising session notes, labs, preparing own notes. 1 Hour for practicing course assignments and labs.
Yes. It is possible to get job in VLSI even with few years gap after graduation. You need a right guidance.
Yes. 2 Years is short span, so with right set of projects and right skill set, you will find opportunities in VLSI
Yes, we do have.
• Ideally, we do not suggest anyone to undergo 2 weeks training, because training requires repeated interactions between trainer and student.
• 2 weeks of time will not give time to complete the assignments, it is most important aspects of the course
• Yes, you can complete. However your preparation may not be up to mark.
• Do not register for complete VLSI training course. • You should start of by opting for basics course(for front end it is Verilog and Advanced Digital design, for Backend it is Physical design basics training). If you find these courses interesting, then you should opt for complete VLSI training course. Many institutes might not offer training only in Verilog, but you should insist, because once you pay the fee for complete course, they will not refund. • If you do course in VLSI basics by spending less fee, you will still have option to pursue with VLSI or look for career in other domain.
• For a fresher salary can be anywhere from 2.5 Lakhs to 6 Lakhs. Product companies do offer up to 15 Lakhs, but they mostly hire from campus.
• All the courses are offered in both classroom and online. Online sessions are done using live gotomeeting training. Student attending online will get the same support as students from classroom.
Yes. Institute is open from 7AM to 9PM on all days. We strong recommend every student to prepare at institute. • Being at institute offers lot of benefits • Unlimited access to recorded videos from the course • Mentor guidance • Clarify doubts right away • Compare your preparation level with other students • Group discussions among other students
Yes. It is strongly recommended to stay close by institute. There are many Paying guests (PGs) available nearby institute (within 1KM).
All courses are already offered at a lowest possible fee. Discount is offered to students from BPL economic status.
Course material, labs, assignments Doubts clarifications Unlimited access to course videos while at institute* Option to repeat the course Dedicated mentor
Yes. At least 20% of students in every batch are from US. We keep majority of our course timings in sync with students from US. In general we try to schedule all courses in morning timings between 6AM to 12PM, India time.
We offer courses custom designed for students planning to pursue MS. Course comes with lot of flexibility in mode of training. Student can attend part of the course in class room, rest online from USA as required.