DFT Training

DFT(Design for Testability) involves using SCAN, ATPG and BIST techniques to add testability to Hardware design. These techniques are targeted towards making it easier to develop and apply tests to the manufactured hardware. There tests in turn help catch manufacturing defects like stuck at 0, 1 faults, etc.

DFT Training will focus on all aspects of testability flow including testability basics, SOC Scan Architecture, different scan types, ATPG DRC Debug, ATPG Simulation debug, and DFT diagnosis. DFT Training course will also focus on JTAG, MemoryBIST, LogicBIST, Scan and ATPG, test compression techniques and Hierarchical scan design.

As part of DFT Training, a complex design example with variety of memories spread around the design used as a reference for learning all testability. While MBIST used to test memories. Boundary scan is a requirement for designs, used to control the MBIST controllers that are created to minimize the need for having extra external pins to run the memory tests.  ATPG test patterns will be created for various different fault models like stuck-at, transition delay, path delay fault models. Various TestKompress techniques will be used to compress test patterns to ensure patterns can be applied on minimal number of IO pins used during test. Compressed test patterns will run more quickly on the production test floor and require less tester memory. Patterns are validated through Simulations.

DFT Training course is designed as per the current industry requirements with multiple hands on projects based on Scan, ATPG and MBIST. DFT Training will help student with in-depth knowledge of all testability techniques. Hands-on project will involve creating large number of test cases for various aspects like Scan insertion, Compression and ATPG pattern generation using MentorGraphics Tessent tool.  More importance is given to basic concepts, interaction sessions, hands-on, important notes and assignments.

MentorGraphics Tessent tool will be used for training. As per survey, it is used by more than 80% companies for DFT. Student will have access to tool for during the course, with provision to extend beyond. Student will get access to tool both at institute and has option to connect to servers from home using VPN.

Student will also get access to Synopsys tool suite.

Design For Testability