After completing this training, you will know how to:

• Utilisation of the primary 7 series FPGA architecture resources
• Project Manager to start a new project
• Identify the available Vivado IDE design flows (project based and non-project batch)
• Identify file sets (HDL, XDC, simulation)
• Analyse designs by using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer.
• Synthesize and implement an HDL design
• Utilise the available synthesis and implementation reports to analyse a design (utilisation, timing, power, etc.)
• Build custom IP with the IP Library utility
• Make basic timing constraints
• Describe and analyse common STA reports
• Identify synchronous design techniques
• Describe how an FPGA is configured

PROJECTS & LABS

• Lab 1: Vivado IDE – create a simple HDL design and simulate the design using the HDL simulator available in Vivado design suite. Generate the bit stream and debug the design using Vivado Logic Analyzer.
  • FPGA simulation and generating the bit stream of combinational and sequential circuits, memories, and registers through the Vivado IDE
  • FPGA design of Synchronous and Asynchronous FIFO.
  • FPGA design of a I2C protocol
  • FPGA design of a SPI protocol
• Lab2:Vivado IP integrator. Vivado project and use IP Integrator to develop a basic embedded system for a target board.Extending the Embedded System into Programmable Logic
  • a. Adding Peripherals in Programmable Logic. Extend the hardware system by adding AXI peripherals from the IP catalog. Adding Your Own IP Peripheral
• Lab 3: Creating and Adding Your Own Custom IP.Use the Manage IP feature of Vivado to create a custom IP and extend the system with the custom peripheral.
• Lab 4: Software Development Environment. Writing Basic Software Applications. Write a basic C application to access the peripherals.
• Lab 5: Software Development and Debugging Software Debugging Using SDK.Use API to drive CPU’s timer. Perform software debugging using SDK.
• Lab 6: Debugging using Chip scope-Vivado Logic Analyzer cores insert various Vivado Logic Analyzer cores to debug/analyze system behavior.
• Lab7.Software Application Discussion about the Possible Applications using Zynq AP SOC
• Lab 8.Installing and running Linux. Installing Petalinux and Booting

Board used in the course

• ZYNQ Processor
  • 667 MHz dual-core Cortex-A9 processor
  • DDR3L memory controller with 8 DMA channels and 4 High Performance AXI3 Slave ports
  • High-bandwidth peripheral controllers: 1G Ethernet, USB 2.0, SDIO
  • Low-bandwidth peripheral controllers: SPI, UART, CAN, I2C
  • Programmable from JTAG, Quad-SPI flash, and microSD card
  • Programmable logic equivalent to Artix-7 FPGA
• Memory
  • 1 GB DDR3L with 32-bit bus @ 1066 MHz
  • 16 MB Quad-SPI Flash with factory programmed 128-bit random number and 48-bit globally unique EUI-48/64™ compatible identifier
  • microSD slot
• Power
  • Powered from USB or any 5V external power source
• USB and Ethernet
  • Gigabit Ethernet PHY
  • USB-JTAG Programming circuitry
  • USB-UART bridge
  • USB 2.0 OTG PHY with host and device support
• Audio and Video
  • Pcam camera connector with MIPI CSI-2 support
  • HDMI sink port (input) with CEC (Zybo Z7-20) and without CEC (Zybo Z7-10)
  • HDMI source port (output) with CEC
  • Audio codec with stereo headphone, stereo line-in, and microphone jacks
• Switches, Push-buttons, and LEDs
  • 6 push-buttons (2 processor connected)
  • 4 slide switches
  • 5 LEDs (1 processor connected)
  • 2 RGB LEDs (Zybo Z7-20) and 1 RGB LED (Zybo Z7-10)
• Expansion Connectors
  • 6 Pmod ports (Zybo Z7-20) and 5 Pmod Ports (Zybo Z7-10)
    • 8 Total Processor I/O
    • 40 Total FPGA I/O (Zybo Z7-20) and 32 (Zybo Z7-10)
    • 4 Analog capable 0-1.0V differential pairs to XADC

Zynq FPGA finds extensive applications in the following.

• Automotive applications
• Computer architecture
• Embedded Linux OS development
• Embedded processing systems
• Hardware/software co-design.
• Build and include hardware accelerators to meet bandwidth demanding applications